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Adapting a Testbench for Fixed-Point Conversion - LabVIEW NXG 3.1 FPGA Module Manual www.ni.com/documentation/en/labview-fpga-module/3.1/fpga-targets/adapt-testbench-fxp-conversion/
When converting a floating-point design to fixed-point, you can adapt an existing testbench, such as the testbench used to test the original floating-point design, to test the output of the converted fixed-point ...

Profiling Code to Convert to Fixed-Point - LabVIEW NXG 3.1 FPGA Module Manual www.ni.com/documentation/en/labview-fpga-module/3.1/fpga-targets/profile-code-convert-fxp/
Profile a design to display fixed-point conversion metrics that you use to analyze and adjust data types when converting to fixed-point. When you profile code, the Convert to Fixed-Point tab displays a ...

Instantiating External FPGA IP in an FPGA Application using the External FPGA IP Node - LabVIEW NXG 3.1 FPGA Module Manual www.ni.com/documentation/en/labview-fpga-module/3.1/fpga-targets/instantiate-ip-in-fpga-using-eip-node/
Integrate external FPGA IP into your FPGA application by placing the External FPGA IP Node into Clock-Driven Logic within your FPGA VI. Before you can add the External FPGA IP Node to your FPGA application, ...

Transferring Data between a Target and Host Using FIFOs - LabVIEW NXG 3.1 FPGA Module Manual www.ni.com/documentation/en/labview-fpga-module/3.1/fpga-targets/transferring-data-target-host-fifo/
Before completing this task, verify that FIFOs are the best data storage and transfer option for your application. Use FIFOs to transfer data between an FPGA target and a host processor without data loss. ...

Monitoring the Compilation of a Bitfile - LabVIEW NXG 3.1 FPGA Module Manual www.ni.com/documentation/en/labview-fpga-module/3.1/fpga-targets/monitoring-bitfile-compilation/
An FPGA target contains a limited number of resources. If a bitfile requires more resources than the FPGA target has available, the compilation of the bitfile fails. Use the estimated and actual number ...

Implementing a Line Buffer for Window-Based Image Processing - LabVIEW NXG 3.1 FPGA Module Manual www.ni.com/documentation/en/labview-fpga-module/3.1/fpgaip-prog/implementing-line-buffer/
You can use an Optimized FPGA VI to implement a line buffer for window-based image processing, useful for Sobel Filters, convolution, and similar operations. This recommended design is optimized to achieve ...

Using Handshaking to Ensure Valid Data in a Clock-Driven Loop - LabVIEW NXG 3.1 FPGA Module Manual www.ni.com/documentation/en/labview-fpga-module/3.1/cdl-prog/handshaking-valid-data-cdl/
Clock-Driven Loops force nodes to return data every clock cycle. However, some nodes, called multi-cycle nodes, need more than one cycle to compute a valid result. Therefore, nodes that depend on data ...

Creating an External FPGA IP Document from an IP-XACT File - LabVIEW NXG 3.1 FPGA Module Manual www.ni.com/documentation/en/labview-fpga-module/3.1/fpga-targets/create-eip-document-from-ip-xact/
Integrate IP into your FPGA application by importing IP descriptions from an IP-XACT XML file into an EIP document, declaring IP files in a project for use as component-level IP (CLIP) or the External ...

Transferring Data between Clock Domains Using Registers - LabVIEW NXG 3.1 FPGA Module Manual www.ni.com/documentation/en/labview-fpga-module/3.1/fpga-targets/transferring-data-clock-domians-registers/
Before completing this task, verify that registers are the best data storage and transfer option for your application. When you need to store a single unit of data per clock cycle and do not require lossless ...

Setting up an FPGA Compile Farm - LabVIEW NXG 3.1 FPGA Module Manual www.ni.com/documentation/en/labview-fpga-module/3.1/fpga-targets/setting-up-an-fpga-compile-farm/
As the administrator of an FPGA compile farm, you must set up a web server on the compile server and connect one or more compile workers to the compile server. Before you begin the setup process, gain ...