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Using Handshaking to Ensure Valid Data in a Clock-Driven Loop - LabVIEW NXG 3.1 FPGA Module Manual www.ni.com/documentation/en/labview-fpga-module/3.1/cdl-prog/handshaking-valid-data-cdl/
Clock-Driven Loops force nodes to return data every clock cycle. However, some nodes, called multi-cycle nodes, need more than one cycle to compute a valid result. Therefore, nodes that depend on data ...

Compiling FPGA Code - LabVIEW NXG 3.1 FPGA Module Manual www.ni.com/documentation/en/labview-fpga-module/3.1/fpga-targets/compiling-fpga-code/
To run code on an FPGA, you must compile the FPGA code into a bitfile that you then deploy to the FPGA. The bitfile contains binary data that describes how to configure the FPGA circuit so that it performs ...

Creating an External FPGA IP Document from IP Source Files - LabVIEW NXG 3.1 FPGA Module Manual www.ni.com/documentation/en/labview-fpga-module/3.1/fpga-targets/create-eip-document-from-hdl-source/
Integrate IP into your FPGA application by creating an External FPGA IP document that declares IP files in a project for instantiation as component-level IP (CLIP) or an External FPGA IP Node. If you want ...

Converting Data Types to Fixed-Point for Implementation on an FPGA - LabVIEW NXG 3.1 FPGA Module Manual www.ni.com/documentation/en/labview-fpga-module/3.1/fpga-targets/converting-to-fxp-for-fpga/
Because resources are limited on an FPGA, convert floating-point data types in your application to fixed-point to conserve resources when you implement the application on an FPGA. Before you convert the ...

Creating a Testbench to Test a Floating-Point Design - LabVIEW NXG 3.1 FPGA Module Manual www.ni.com/documentation/en/labview-fpga-module/3.1/fpga-targets/create-testbench-flp-design/
Use a testbench to test the output of your floating-point design and ensure the results are what you expect. A testbench is typically a VI that provides simulated input values to your code and displays ...

Creating an External FPGA IP Document from an IP-XACT File - LabVIEW NXG 3.1 FPGA Module Manual www.ni.com/documentation/en/labview-fpga-module/3.1/fpga-targets/create-eip-document-from-ip-xact/
Integrate IP into your FPGA application by importing IP descriptions from an IP-XACT XML file into an EIP document, declaring IP files in a project for use as component-level IP (CLIP) or the External ...

Creating Custom Condition Symbols for an FPGA Target - LabVIEW NXG 3.1 FPGA Module Manual www.ni.com/documentation/en/labview-fpga-module/3.1/fpga-targets/custom-condition-symbol/
You can create custom condition symbols targeted to an FPGA and use these symbols in any Disable Structure within your FPGA application. In SystemDesigner, select the FPGA target. On the Item tab, in the ...

Downloading and Running an FPGA VI - LabVIEW NXG 3.1 FPGA Module Manual www.ni.com/documentation/en/labview-fpga-module/3.1/fpga-targets/downloading-running-fpga-vi/
To complete this task, you'll need a host VI and a compiled bitfile for the FPGA VI. Use the FPGA Host Interface nodes to download, run, and communicate with code on the FPGA. What to Use Open FPGA VI ...

Increasing Execution Rate of Code on an FPGA - LabVIEW NXG 3.1 FPGA Module Manual www.ni.com/documentation/en/labview-fpga-module/3.1/fpga-targets/increasing-fpga-execution/
If the FPGA target base clocks fail to execute code at a rate that meets the timing objectives of your application, you can create a derived clock to achieve faster execution rates. Complete the following ...

Integrating External FPGA IP into an FPGA Application - LabVIEW NXG 3.1 FPGA Module Manual www.ni.com/documentation/en/labview-fpga-module/3.1/fpga-targets/integrate-external-ip-into-fpga/
By integrating external FPGA IP into an FPGA application, you can reuse existing FPGA code to implement a wide range of algorithms that are optimized for FPGAs. The Xilinx CORE Generator IP palette contains ...